Design Techniques for Gate-Leakage Reduction in CMOS Circuits
نویسندگان
چکیده
Oxide tunneling current in MOS transistors is fast becoming a non-negligible component of power consumption as gate oxides get thinner, and could become in the future the dominant leakage mechanism in sub-100nm CMOS circuits. In this paper, we present an analysis of static CMOS circuits from a gate-leakage point of view. We first consider the dependence of the gate current on various conditions for a single transistor, and identify 3 main regions in which a MOS transistor will operate between clock transitions. The amount of gate-current differs by several orders of magnitude from one region to another. Whether a transistor will leak significantly or not is determined by its position in relation to other transistors within a structure. By comparing logically equivalent but structurally different CMOS circuits, we find that the gate current exhibits a ‘structure dependence’. Also, the total gate-leakage in a given structure varies significantly for different combinations of inputs, from which we derive “state-dependent gate-leakage tables” that can be used to estimate the total amount of gate-current for a large circuit. Finally, we suggest guidelines aimed at reducing the amount of oxideleakage current based on the presented structure and state dependencies.
منابع مشابه
Analysis and Mitigation of Cmos Gate Leakage
Conventional leakage reduction techniques focus primarily on sub-threshold leakage mitigation, while neglecting the effect of gate leakage current. This work focuses on understanding gate leakage current and developing circuit techniques for total leakage minimization. We present an efficient technique for gate leakage of CMOS circuits. Input vector control and circuit reconfiguration technique...
متن کاملLeakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits
High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper r...
متن کاملLeakage Reduction of Scaled CMOS Circuits Using Efficient Control Point Insertion Technique
Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage components of such circuits are the sub threshold leakage and the thin-oxide gate leakage. This paper describes an efficient leakage reduction method that considers both these components, and is based on the selective insertion of control points. The selection is based on the leakage...
متن کاملReduction of Leakage Power using Stacking Power Gating Technique in Different CMOS Design Style at 45Nanometer Regime
As transistor sizes scale down and levels of integration increase, leakage power has become a vital downside in modern low-power VLSI technology. This is often very true for ultra-lowvoltage (ULV) circuits, wherever high levels of leakage force designers to selected relatively high threshold voltages, which limits performance. In this paper, we design different design approach of master slave D...
متن کاملGaleorstack- A Novel Leakage Reduction Technique for Low Power VLSI Design
Leakage power consumption plays a significant role in current CMOS technology. International Technology Roadmap for semiconductors reports that leakage power consumption dominates the total chip power consumption as technology advances to nano scale. Most of the battery operated applications such as cell phones, Laptops etc requires a longer battery life, which can be made possible by controlli...
متن کامل